1. Field of the Invention
The present invention relates to a driving method of an organic electroluminescence emission part.
2. Description of Related Art
A display element having an emission part and a display device including the display element are known. For example, a display element having an organic electroluminescence emission part (hereinafter, may be abbreviated simply as “organic EL display element”) using electroluminescence (hereinafter, may be abbreviated as “EL”) of an organic material attracts attention as a display element that can perform high-luminance emission by low-voltage direct-current drive.
Like in a liquid crystal display device, for example, in an organic electroluminescence display device (hereinafter, may be abbreviated simply as “organic EL display device”) including an organic EL display element, a simple matrix system and an active matrix system are known as drive systems. The active matrix system has a disadvantage that the structure becomes complex, but has advantages that image luminescence can be made higher etc. In the organic EL display element driven by the active matrix system, an emission part including an organic layer containing an emission layer etc. and a drive circuit for driving the emission point are provided.
As a circuit for driving an organic electroluminescence emission part (hereinafter, may be abbreviated simply as “emission part”), a drive circuit including two transistors and one capacity part (referred to as “2Tr/1C” drive circuit) is known from JP-A-2007-310311, for example. The 2Tr/1C drive circuit includes two transistors of a writing transistor TRW and a driving transistor TRD, and further includes one capacity part C1 as shown in FIG. 2. Here, the other source/drain region of the driving transistor TRD forms a second node ND2, and the gate electrode of the driving transistor TRD forms a first node ND1.
Further, as shown in a timing chart of FIG. 4, in [period-TP(2)1′], preprocessing for threshold voltage cancel processing is executed. That is, via the writing transistor TRW in ON-state by a signal from a scan line SCN, a first node initializing voltage V0fs (e.g., zero volt) is applied from a data line DTL to the first node ND1. Thereby, the potential of the first node ND1 becomes V0fs. Further, via the driving transistor TRD, a second node initializing voltage VCC-L, (e.g., −10 volts) is applied from a power supply part 100 to the second node ND2. Thereby, the potential of the second node ND2 becomes VCC-L. The threshold voltage of the driving transistor TRD is expressed by a voltage Vth (e.g., 3 volts). When the potential difference between the gate electrode and the other source/drain region of the driving transistor TRD (hereinafter, may be referred to as “source region” for convenience) becomes Vth or more, the driving transistor TRD turns into ON-state. Note that the cathode electrode of the emission part ELP is connected to a power supply line PS2 to which a voltage VCat (e.g., zero volts) is applied.
Then, threshold voltage cancel processing is performed in [period-TP(2)2′]. That is, while the ON-state of the writing transistor TRW is maintained, the voltage of the power supply part 100 is switched from the second node initializing voltage VCC-L to a drive voltage VCC-H (e.g., 20 volts). As a result, the potential of the second node ND2 changes toward the potential obtained by subtracting the threshold voltage Vth of the driving transistor TRD from the potential of the first node ND1. That is, the potential of the floating second node ND2 rises. Then, when the potential difference between the gate electrode and the source region of the driving transistor TRD reaches Vth, the driving transistor TRD turns into OFF-state. In the state, the potential of the second node ND2 is generally (V0fs−Vth).
Then, in [period-TP(2)3′], the writing transistor TRW is turned into OFF-state. Then, the voltage of the data line DTL is set to the voltage corresponding to a video signal [video signal (drive signal, luminance signal) VSig_m for controlling the luminance in the emission part ELP].
Then, in [period-TP(2)4′], writing processing is performed. Specifically, the scan line SCN is turned into HIGH-level and the writing transistor TRW is turned into ON-state. As a result, the potential of the first node ND1 rises to the video signal VSig_m.
Here, given that the value of the capacity part C1 is c1, the value of the capacity CEL of the emission part ELP is cEL, and further, the value of the parasitic capacity between the gate electrode and the other source/drain region of the driving transistor TRD is cgs, when the potential of the gate electrode of the driving transistor TRD changes from V0fs to VSig_m (>V0fs), the potentials at ends of the capacity part C1 (in other words, the potentials of the first node ND1 and the second node ND2) basically change. That is, the charge based on the amount of change (VSig_m−V0fs) of the potential of the gate electrode of the driving transistor TRD (=potential of the first node ND1) is assigned to the capacity part C1, the capacity CEL of the emission part ELP, and the parasitic capacity between the gate electrode and the other source/drain region of the driving transistor TRD. Hence, if the value cEL is a sufficiently large value compared to the value c1 and the value cgs, the change of the potential of the other source/drain region of the driving transistor TRD (second node ND2) according to the amount of change (VSig_m−V0fs) of the potential of the gate electrode of the driving transistor TRD is small. Further, typically, the value cEL of the capacity CEL of the emission part ELP is larger than the value c1 of the capacity part C1 and the value cgs of the parasitic capacity of the driving transistor TRD. Accordingly, for convenience of explanation, the explanation will be made without consideration of the potential change of the second node ND2 generated by the potential change of the first node ND1. Note that the drive timing chart shown in FIG. 4 is formed without consideration of the potential change of the second node ND2 generated by the potential change of the first node ND1.
In the above described operation, while the voltage VCC-H is applied from the power supply part 100 to one source/drain region of the driving transistor TRD, the video signal VSig_m is applied to the gate electrode of the driving transistor TRD. Accordingly, as shown in FIG. 4, in [period-TP(2)4′], the potential of the second node ND2 rises. The amount of rise of the potential ΔV (potential correction value) will be described later. Given that the potential of the gate electrode of the driving transistor TRD (first node ND1) is Vg, and the potential of the other source/drain region of the driving transistor TRD (second node ND2) is Vs, if the amount of rise of the potential ΔV of the second node ND2 is not considered, the value of Vg and the value of Vs are as follows. The potential difference between the first node ND1 and the second node ND2, i.e., the potential difference Vgs between the gate electrode and the other source/drain region serving as a source region of the driving transistor TRD can be expressed by the following expressions (A).Vg=VSig_m Vs≈V0fs−Vth Vgs≈VSig_m−V0fs−Vth)  (A)
That is, Vgs obtained in the writing processing in the driving transistor TRD depends only on the video signal VSig_m for controlling the luminance in the emission part ELP, the threshold voltage Vth of the driving transistor TRD, and the voltage V0fs for initializing the potential of the gate electrode of the driving transistor TRD. Further, it is independent of the threshold voltage Vth-EL of the emission part ELP.
Subsequently, mobility correction processing will be briefly explained. In the above described operation, in the writing processing, mobility correction processing of changing the potential of the other source/drain region of the driving transistor TRD (i.e., the potential of the second node ND2) according to the characteristic of the driving transistor TRD (e.g., magnitude of mobility μ or the like) is also performed.
As described above, while the voltage VCC-H is applied from the power supply part 100 to one source/drain region of the driving transistor TRD, the video signal VSig_m, is applied to the gate electrode of the driving transistor TRD. Here, as shown in FIG. 4, in [period-TP(2)4′], the potential of the second node ND2 rises. As a result, if the value of the mobility μ of the driving transistor TRD is large, the amount of rise of the potential ΔV (potential correction value) in the source region of the driving transistor TRD becomes larger, and, if the value of the mobility μ of the driving transistor TRD is small, the amount of rise of the potential ΔV (potential correction value) in the source region of the driving transistor TRD becomes smaller. The potential difference Vgs between the gate electrode and the source region of the driving transistor TRD is transformed from the expression (A) to the following expression (B). Note that, the whole time (t0) of the [period-TP(2)4′] may be determined in advance as a design value at designing of the organic EL display device.Vgs≈VSig_m−(V0fs−Vth)−ΔV  (B)
Through the above operation, the threshold voltage cancel processing, the writing processing, and the mobility correction processing are completed. Further, at the start of the subsequent [period-TP(2)5′], the writing transistor TRW is turned into OFF-state by the signal from the scan line SCL, and thereby, the first node ND1 is floated. Concurrently, the voltage VCC-H is applied from the power supply part 100 to one source/drain region of the driving transistor TRD (hereinafter, may be referred to as “drain region” for convenience). Therefore, as a result, the potential of the second node ND2 rises, the same phenomenon as that in a so-called bootstrap circuit occurs in the gate electrode of the driving transistor TRD, and the potential of the first node ND1 also rises. The potential difference Vgs between the gate electrode and the source region of the driving transistor TRD basically holds the value of the expression (B). Further, the current flowing in the emission part ELP is a drain current Ids flowing from the drain region to the source region of the driving transistor TRD. If the driving transistor TRD ideally operates in the saturation region, the drain current Ids can be expressed by the following expression (C). The emission part ELP emits light with luminescence according to the value of the drain current Ids. The coefficient k will be described later.Ids=k·μ·(Vgs−Vth)2 =k·μ·(VSig_m−V0fs−ΔV)2  (C)
Further, [period-TP(2)5′] shown in FIG. 4 is an emission period and a period from the start of [period-TP(2)6′] to the next emission period is a non-emission period (hereinafter, may be referred simply to as “non-emission period”). Specifically, at the start of [period-TP(2)6′], the voltage VCC-H of the power supply part 100 is switched to the voltage VCC-L and maintained to the end of the next period [period-TP(2)1′] (shown by [period-TP(2)+1′] in FIG. 4). Thereby, the period from the start of [period-TP(2)6′] to the start of the next [period-TP(2)+5′] is the non-emission period.
The operation of the 2Tr/1C drive circuit, which has been briefly explained, will be specifically explained later.